`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:36:02 01/12/2011 
// Design Name: 
// Module Name:    alu 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module alu#(parameter WIDTH = 8)
(
    // Incoming inputs from the register file
    input [WIDTH - 1 : 0] v1_in,
    input [WIDTH - 1 : 0] v2_in,

    // Opcode of the operation to perform (derived from the ISA)
    input [1 : 0] alu_op_code_in,

    // Result of the given operation
    output reg [WIDTH - 1 : 0] result_out
    
);

parameter ADD = 2'd1, 
			 SUB = 2'd2, 
			 MULT = 2'd3;

always@(*)
	begin
		case (alu_op_code_in)
		ADD:    result_out = v1_in + v2_in;
		SUB: result_out = v1_in - v2_in;
		MULT: result_out = v1_in * v2_in;
	end
        
end module 
